1. Field of the Invention
The present invention relates to a duty cycle controller and, more particularly, to an automatic duty cycle controller for an ultra high-speed digital multiplexer.
2. Description of Related Art
Digital multiplexers are widely used in time division multiplexing systems. Typically, such a digital multiplexer will include a logic circuit with components such as gates and flip-flops. For example, a prior art 2:1 multiplexer with a non-return-to-zero (xe2x80x9cNRZxe2x80x9d) format output interleaves two relatively low-frequency digital input signals using a high-speed clock. A logic circuit samples the input signals at a rate determined by the clock signal and interleaves the signals. A typical low-speed prior art multiplexer includes a D-type flip-flop that re-times the output signal to remove any imperfections that may have occurred during interleaving. That is, the multiplexed signal is passed through a D-type flip-flop under the control of the clock signal used to sample the data signals for multiplexing. The D-type flip-flop thus provides the two interleaved signals with a precisely controlled 50% duty cycle.
However, as the speed of the multiplexer (the frequency of the clock signals) increases, it becomes increasingly difficult to provide the multiplexed output signal with a 50% duty cycle. A major source of difficulty is that the operation of D-type flip-flops degrades at a frequency above about 10 GHz. Consequently, higher-speed multiplexers often omit the D-type flip-flop. Unfortunately, this degrades the multiplexer output because of imperfect multiplexing by the logic circuit that performs the interleaving operation. That is, without the D-type flip-flop, the interleaving imperfections introduced by the logic circuit remain in the output.
The most common imperfection is output duty cycle offset caused by drift in the logic circuit. The problems caused by this phenomenon have particularly serious consequences in communication systems because it causes a serious strain on the transmission signal. For example, in an optical fiber communications system using an NRZ data format it is critical that the interleaved signals have a uniform duty cycle. If they do not, severe difficulties arise in decoding the signal at its destination.
A high-speed multiplexed signal is illustrated in FIG. 2, which shows the output from a prior art 2:1 multiplexer operating at 20 GHz without a D-type flip-flop. It will be appreciated that duty cycle of this signal varies over time, in that the pulse width Wa is shorter than the pulse width wb. As a result, the output signal is degraded in terms of its signal-to-noise ratio, inter-symbol interference and its timing margin. All of these properties of the signal are important in accurately reproducing the original signal at the signal""s destination.
Consequently, there is a need to be able to control the output signal duty cycle in a multiplexer operating at a frequency greater than the operational speed of a D-type flip-flop, and achieve an equal and stable pulse width in each time slot of the multiplexed signal.
It is an object of the present invention to provide automatic duty cycle control in an ultra high-speed digital multiplexer.
In accordance with one aspect of the invention, a duty cycle controller for a multiplexer using a comparator for providing at an output of the multiplexer two interleaved data signals by comparing a clock signal having a predetermined frequency to a comparator set point comprises a bandpass filter for providing to an output a signal having a frequency substantially equal to the frequency of the clock signal, the bandpass filter having an input for connection to the output of the multiplexer, a power detector having an input for accepting the bandpass filter output signal and providing at an output of the power detector a signal indicating the power level of the bandpass filter output signal, and an integrator for integrating the power detector output signal over a predetermined period of time and providing a reference signal for adjusting the set point of the comparator.
In accordance with another aspect of the invention, a multiplexer comprises a comparator for outputting two interleaving signals by comparing a clock signal having a predetermined frequency to a comparator set point, a logic circuit for outputting a multiplexed signal by using the interleaving signals to interleave two data signals input to the logic circuit, a bandpass filter for accepting the logic circuit output and providing to an output of the bandpass filter a signal comprising components of the logic circuit output signal having a frequency substantially equal to the frequency of the clock signal, a power detector having an input for accepting the bandpass filter output signal and providing at an output of the power detector a signal indicating the power level of the bandpass filter output signal, and an integrator for integrating the power detector output signal over a predetermined period of time and providing a reference signal used to adjust the set point of the comparator.
According to yet another aspect of the present invention, a method for controlling the duty cycle of a multiplexer using a comparator for providing at an output of the multiplexer two interleaved data signals by comparing a clock signal having a predetermined frequency to a comparator set point comprises the steps of filtering the output of the multiplexer to provide a filtered signal having a frequency substantially equal to the frequency of the clock signal, detecting the power of the filtered signal, and integrating the power of the filtered signal over a predetermined period of time to provide a reference signal for adjusting the set point of the comparator.